1. Field of the Invention
The present invention relates to a timing recovery, and more particularly, to a timing recovery apparatus and method for detecting a timing lock and deviation for a timing recovery of a digital broadcasting receiver.
2. Discussion of the Related Art
Generally, since a symbol synchronization block of a Quadrature Amplitude Modulation (QAM) receiver, which is selected as a transmission standard of a digital TV cable channel, generates a clock of a symbol string, it is called a clock synchronizer or clock generator.
An object of symbol synchronization is to right and accurately estimate a symbol transition time in a receiver on the basis of received data string.
Accordingly, the symbol synchronization is necessarily required for a demodulation process of a digital communication, and employs a lock detector to obtain better convergence characteristic.
A function of the symbol synchronizer having the lock detector is described as follows.
FIG. 1 is a block diagram illustrating a construction of a general Quadrature Amplitude Modulation (QAM) demodulator having the lock detector.
As shown in FIG. 1, the QAM demodulator includes a multiplier 1 for multiplying an input signal by a predetermined frequency signal outputted from a Numerically Controlled Oscillator (NCO) 5, to output a baseband signal; a resampler 2 for receiving and sampling the baseband signal outputted from the multiplier 1; a baseband signal processor 3 for receiving the signal from the resampler 2 to perform a signal process such as decoding; a carrier synchronizer and channel equalizer 4 for performing a distortion compensation of the signal outputted from the baseband signal processor 3; a numerically controlled oscillator 5 for outputting a signal having a frequency for obtaining an accurate baseband signal by an error detected in the carrier synchronizer and channel equalizer 4; a symbol synchronizer for rightly estimating a symbol transition time at the signal of the baseband signal processor 3; and the lock detector 7 for detecting a convergence state of the symbol synchronizer 6 to control a bandwidth.
Here, the symbol synchronizer 6 is disposed at a front of the carrier synchronizer and channel equalizer 4 to transmit synchronized symbol data to the carrier synchronizer and channel equalizer 4.
Accordingly, the convergence characteristic of the symbol synchronization has influence on the convergence characteristic of the carrier synchronizer and channel equalizer 4.
Therefore, the convergence characteristic of the symbol synchronizer 6 requires a fast initial synchronization capture and a weak jitter characteristic of a normal state.
For the fast synchronization capture, a symbol synchronization loop (timing recovery loop) should have a wide loop bandwidth. For obtaining the weak jitter characteristic at the normal state, the symbol synchronization loop should have a narrow loop bandwidth.
For obtaining the above convergence characteristic, the synchronization is initially captured at the wide loop band, and when the convergence is made at the normal state, the lock detector 7 is used to gradually narrow the loop bandwidth (called “gear shifting”).
Further, in order to obtain the convergence characteristic of a more fast and accurate receiver convergence characteristic in association with the carrier synchronizer and channel equalizer 4, information on the convergence state of the symbol synchronization loop is required.
Accordingly, the lock detector 7 is essential for improving and stabilizing a performance of the receiver, and the lock detector 7 necessarily requires a function of accurate detection.
A conventional lock detecting algorithm and construction of the lock detector is described with reference to FIG. 2 as follows.
FIG. 2 is a block diagram illustrating a conventional timing lock detector.
As shown in FIG. 2, the baseband signal inputted to the symbol synchronizer 6 is inputted to a Timing Error Detector (TED) 61 included in the symbol synchronizer 6.
In a Quadrature Phase Shift Keying (QPSK) or a Quadrature Amplitude Modulation (QAM) system, the timing error detector 61 of the symbol synchronizer 6 calculates an error from the baseband signal since a timing frequency and phase offset is generated while the baseband signal passes through a channel of an analogue unit of a transceiver.
The calculated error is accumulated in an integrator (not shown) of a loop filter 63 to control a Number Controlled Oscillator (NCO) or a Voltage Controlled Oscillator (VCO) 65, thereby recovering the symbol synchronization.
At this time, since the loop bandwidth of a closed loop comprised of the resampler 2 and the symbol synchronizer 6 is proportional to a gain of the closed loop, the gain of the closed loop is stepwise controlled by using the timing lock detector 7, to control the loop bandwidth.
The timing lock detector 7 of FIG. 2 is connected to the loop filter 63 to obtain a variance of an error value (X) accumulated in the integrator of the loop filter 63 so that the obtained variance is compared with a fixed threshold value in a comparator 71 to judge a lock time.
The lock signal is transmitted to the lock controller 73 to allow the selection of the loop bandwidth of the closed loop.
FIG. 3 is a view illustrating a principle of a conventional lock detector. FIG. 3A illustrates a convergence curve for a timing offset, and FIG. 3B illustrates a variance of a convergence curve for the timing offset.
Referring to FIG. 3A, after the convergence of a reference timing offset frequency, a magnitude of a remaining jitter gets different depending on a channel state (SNR) at the normal state.
Referring to FIG. 3B, the error value (X) accumulated in the integrator of the loop filter is converged depending on the channel state (SNR), the variance of the error value (X) is also varied due to the remaining jitter characteristic inversely proportion to the channel state at the normal state. The variance (Variance X) of the error value (X) is obtained in E[X2]-E[X]2.
Accordingly, the conventional lock detector has a drawback in that a hardware cost is very much paid for the variance calculation, and since the variance is different depending on the channel state after the convergence, the fixed threshold value generates an erroneous lock signal, thereby causing a lock error.
The above lock error does not only extend a convergence time, but also makes it impossible to perform the convergence for a large timing frequency and phase offset.
Of course, an appropriate threshold value is obtained by using a SNR calculator, but there is a drawback in that the convergence time of the symbol synchronizer is lengthened as long as a calculation time of the SNR calculator to make it possible to provide a weak remain characteristic, but to make it impossible to provide the convergence characteristic of the fast synchronization capture, thereby preventing the lock detector from performing its function in orderly fashion.
Further, the conventional timing lock detector, which accumulates and processes a spontaneous symbol error for a predetermined duration, has a drawback in that at the time of the existence of a symbol timing deviation, the timing deviation is minutely generated for a duration larger than the process duration of the timing lock detector, thereby making it impossible to detect the timing deviation.
At this time, a method of increasing the process duration of the conventional timing lock detector can be considered, but it has a drawback in that the delay of the lock judgment is caused to decrease a convergence speed of the receiver.